1. Field of the Invention
The present invention relates to a gate driver-on-array (GOA) integrated into a display panel and method of making the same, and more particularly, to a GOA in which the electrical connection between a first patterned metal layer and a second patterned metal layer is not implemented by a transparent conductive layer, and method of making the same.
2. Description of the Prior Art
Display panels have been broadly applied in electronic displaying devices, e.g. thin film transistor liquid crystal displays (TFT-LCDs), organic light emitting displays (OLEDs), low temperature polycrystalline silicon (LTPS) TFT-LCDs, plasma display panel (PDP) displays, etc. Refer to FIG. 1. FIG. 1 plan view schematically illustrating a conventional TFT-LCD panel. As shown in FIG. 1, the TFT-LCD panel 10 includes pixels 12 arranged as a matrix. The pixels 12 are controlled by a plurality of data line D1, D2, . . . , Dn, and gate lines G1, G2, . . . , Gn. The data lines D1, D2, . . . , Dn are electrically connected to a data driver 14 and driven thereby, and the gate lines G1, G2, . . . , Gn are electrically connected to the gate driver 16 and driven thereby. In addition, the TFT-LCD panel 10 is electrically connected to a printed circuit board (PCB) 18, so that the circuits of the PCB 18 can convert image signals into voltage signals, and deliver the voltage signals to the data driver 14 and the gate driver 16 via a bus line 20.
In recent years, the GOA integrately formed in the display panel, has gradually replaced the traditional external gate driving chip adapted to drive pixels since the number of required devices and the cost can be both reduced. Referring to FIG. 2, there is illustrated a circuit diagram of a GOA integrated into a display panel. As shown in FIG. 2, the GOA is aimed to provide pulse waves having constant timing, and these pulse waves will be delivered to a TFT-LCD panel 10 to control the switching of thin film transistors. The GOA mainly includes a plurality of signal lines (e.g. L1, L2, L3 and L4), a plurality of thin film transistors (e.g. T1, T2, T3 and T4), capacitors (e.g. C1), and conducting wirings (e.g. W1). The signal line L1 is used to transfer a voltage signal Vss, the signal line L2 is used to transfer a start pulse signal Vst, the signal line L3 is used to transfer a clock signal Vck, and the signal line L4 is used to transfer a complementary clock signal Vxck. The purpose of the conducting wiring W1 is to deliver signals of the signal line e.g. the signal line L4 to an internal device such as the thin film transistor T2.
FIG. 3 is a cross-sectional view of a conventional GOA, which is taken along lines A-A′, B-B′, and C-C′ of FIG. 2, respectively. As shown in FIG. 3, the conventional GOA integrated into a display panel is mainly stacked by six thin films including a first patterned metal layer 22, a gate insulating (G1) layer 24, a semiconductor layer 26, a heavily doped semiconductor layer 28, a second patterned metal layer 30, a passivation layer 32, and a transparent conductive layer (pixel electrode) 34. In the GOA structure, part of the first patterned metal layer 22 must be electrically connected to the second patterned metal layer 30 so as to implement required electrical functions. For instance, the signal line L4 defined by the second patterned metal layer 30 is electrically connected to the conducting wiring W1 defined by the first patterned metal layer 22, so that the voltage signal Vck can be delivered to the drain electrode of the thin film transistor T2 via the conducting wiring W1. Also, the gate electrode of the thin film transistor T1 made of the first patterned metal layer 22 must be electrically connected to the drain made of the first patterned metal layer 30.
In the conventional GOA structure, as shown in FIG. 3, the first patterned metal layer 22 and the second patterned metal layer 30 are electrically connected together by forming through holes 32A in the passivation layer 32 and the gate insulating layer 24 disposed thereunder, and by successively filling the transparent conductive layer 34 into the through holes 32A. Accordingly, the first patterned metal layer 22 and the second patterned metal layer 30 are electrically connected. Using the transparent conductive layer 34 to bridge the first patterned metal layer 22 and the second patterned metal layer 30, however, suffers from the following drawbacks. First, through hole corrosion tends to occur in the through hole areas during subsequent processes, and parasitic capacitances may generate in the connection structure. Besides, the connection structure made of the transparent conductive layer is disposed under the sealant, which is liable to cause metal precipitate. This would lead to a poor electrical contact between the first patterned metal layer and the second patterned metal layer, thereby generating wave pulses having abnormal waveform. In addition, using the transparent conductive layer to connect the first patterned metal layer and the second patterned metal layer increases the layout area of the GOA.